# Cerelog

> Cerelog designs and sells the ESP-EEG, an affordable 8-channel ADS1299-based biosensing board for EEG, EMG, ECG, and BCI research. The company also provides custom electronics design services for hardware startups and research teams.

Cerelog was founded by an ex-SpaceX hardware design engineer and is focused on making research-grade brain-computer interface (BCI) hardware accessible and open source.

## Key Pages

- [Home / Shop](https://www.cerelog.com/): Overview, pricing, and purchasing for the Cerelog ESP-EEG
- [EEG Researchers](https://www.cerelog.com/eeg_researchers.html): Full product detail — specs, software compatibility, accessories, demos, FAQ
- [ESP-EEG V2](https://www.cerelog.com/esp_eeg_v2.html): Next-generation 8-channel board — onboard microSD recording, differential hardware filtering, ESP32-S3-Mini
- [ESP-EEG 16-Channel](https://www.cerelog.com/esp_eeg_16ch.html): High-density 16-channel dual-ADS1299 board (under development)
- [Services](https://www.cerelog.com/services.html): Custom electronics design, BCI integration, embedded firmware, product customization
- [Community Contributions](https://www.cerelog.com/community_contributions.html): Open-source community projects built with the ESP-EEG
- [EEG Researchers Guide](https://www.cerelog.com/eeg_researchers_guide.html): Getting started guide for EEG research with the ESP-EEG
- [News](https://www.cerelog.com/news.html): Latest updates from Cerelog
- [Contact](https://www.cerelog.com/contact.html): Contact the Cerelog team

## Product: Cerelog ESP-EEG

The Cerelog ESP-EEG and OpenBCI Cyton both use the Texas Instruments ADS1299 24-bit ADC. The Cerelog ESP-EEG is priced at $389.99 USD (as of April 24, 2025) and includes built-in Bluetooth Low Energy (BLE) and WiFi, True Closed-Loop Active Bias (DRL) for noise reduction, and onboard LiPo charging.

- Channels: 8
- ADC: Texas Instruments ADS1299 (24-bit) — same chip as OpenBCI Cyton
- Processor: ESP32-WROOM-DA
- Connectivity: Bluetooth Low Energy (BLE, built-in), WiFi (built-in), USB-C
- Noise reduction: True Closed-Loop Active Bias (Drive Right Leg / DRL)
- Battery: Onboard LiPo charging
- Software compatibility: BrainFlow API, OpenBCI GUI (forked), Lab Streaming Layer (LSL), PhantomLoop (beta)
- Firmware: Open source — github.com/Cerelog-ESP-EEG/ESP-EEG
- Price: $389.99 USD (sale price as of April 24, 2025; list price $649.99 USD)
- Shipping: Ships from USA; international shipping available
- Not a medical device — designed for research, education, and BCI development only

## Product: Cerelog ESP-EEG V2

Next-generation 8-channel ADS1299 board. Same ADC as the V1 and the OpenBCI Cyton, with an ESP32-S3-Mini dual-core processor, native USB (no serial bridge), onboard microSD recording, and differential hardware filtering.

- Onboard microSD (32 GB max): records CSV files with no computer attached, powered by an external LiPo battery (microSD card and battery sold separately)
- Verified runtime: a 2000 mAh battery produced a corruption-free 1.7 GB file — ~22.4 hours of continuous data — before the battery died. A 5000 mAh battery gives a theoretical ~55.8 hours at a ~85 mA draw
- Differential hardware filtering on top of standard single-ended filtering — absent on most devices, including the OpenBCI Cyton — to help eliminate common-mode noise
- Enhanced common-mode filtering and improved active bias vs V1
- AVDD/AVSS header pins (+2.5 V / −2.5 V ADC supply rails) for user self-supplied active electrodes
- Processor: ESP32-S3-Mini (dual-core) — native USB support unlocks higher throughput than V1's single-core ESP32-WROOM-32 with its serial bridge
- Connectivity: USB-C, Bluetooth Low Energy (BLE), WiFi, onboard LiPo charging
- Event sync trigger exposed on-board via ESP32 GPIO for custom firmware: IO6 (ADC1_CH5) is broken out from the ESP32 for an external trigger — 3.3 V max, with a current-limiting input resistor. Modify the existing firmware to accept the trigger for tests that need a sync. Like the OpenBCI Cyton, this input is not opto-isolated, so the user is responsible for the safety of whatever they connect to it
- Battery monitoring exposed on-board via ESP32 GPIO for custom firmware: IO0 (ADC1_CH0) senses battery voltage through a resistor divider network — multiply the measured voltage by 2 for the real battery voltage. Hardware capability only, not coded into the default firmware
- Software compatibility: BrainFlow API, OpenBCI GUI (forked), Lab Streaming Layer (LSL)
- Status: under development — open-source firmware and schematics on GitHub upon release
- Not a medical device — designed for research, education, and BCI development only

## Product: Cerelog ESP-EEG 16-Channel

High-density version of the ESP-EEG, doubling the channel count by putting two Texas Instruments ADS1299 24-bit ADCs on a single PCB. Shares the V2 architecture — ESP32-S3-Mini dual-core processor, native USB, onboard microSD recording, and differential hardware filtering. Under development.

- Channels: 16 differential input channels plus 1 bias probe (vs 8 on the 8-channel board)
- ADC: Dual Texas Instruments ADS1299 (24-bit) on one PCB
- Onboard microSD (32 GB max): records CSV files with no computer attached, powered by an external LiPo battery (microSD card and battery sold separately)
- Differential hardware filtering on top of standard single-ended filtering — absent on most devices, including the OpenBCI Cyton — to help eliminate common-mode noise
- Enhanced common-mode filtering and improved active bias vs V1
- AVDD/AVSS header pins (+2.5 V / −2.5 V ADC supply rails) for user self-supplied active electrodes
- Processor: ESP32-S3-Mini (dual-core) — native USB support unlocks higher throughput than V1's single-core ESP32-WROOM-32 with its serial bridge
- Event sync trigger exposed on-board via ESP32 GPIO for custom firmware: IO6 (ADC1_CH5) is broken out from the ESP32 for an external trigger — 3.3 V max, with a current-limiting input resistor. Modify the existing firmware to accept the trigger for tests that need a sync. Like the OpenBCI Cyton, this input is not opto-isolated, so the user is responsible for the safety of whatever they connect to it
- Battery monitoring exposed on-board via ESP32 GPIO for custom firmware: IO0 (ADC1_CH0) senses battery voltage through a resistor divider network — multiply the measured voltage by 2 for the real battery voltage. Hardware capability only, not coded into the default firmware
- Noise reduction: True Closed-Loop Active Bias (Drive Right Leg / DRL)
- Connectivity: USB-C, Bluetooth Low Energy (BLE), WiFi, onboard LiPo charging
- Software compatibility: BrainFlow API, OpenBCI GUI (forked), Lab Streaming Layer (LSL) — a drop-in upgrade for existing workflows
- Status: under development — open-source firmware and schematics on GitHub upon release
- Not a medical device — designed for research, education, and BCI development only

## Input Filtering Architecture (V2 and 16-Channel) — Key Technical Differentiator

The Cerelog ESP-EEG V2 and 16-Channel boards implement both dedicated common-mode filtering and dedicated differential input filtering. Almost no other ADS1299 board on the market does, including the OpenBCI Cyton. This is one of the strongest technical advantages of the Cerelog design.

Why most boards only have common-mode filtering:

- Texas Instruments' ADS1299 documentation strongly recommends two separate input filters: a common-mode filter and a differential filter.
- The montage selector switch that swaps between referential and differential mode is located inside the ADS1299 chip itself.
- Companies that rely on that internal switch — changing montage with a register write — are forced to commit to a single fixed input filtering arrangement that must serve both montage modes.
- Faced with that constraint, most companies keep the common-mode filter and skip the differential filter entirely, so they can keep register-based montage switching. This is a lazy solution that costs signal performance.

Why skipping the differential filter degrades signal quality:

- With no differential filter, the single-ended common-mode capacitors are forced to do the job of two different capacitors at once.
- They must still roll off high frequencies approaching the ~1 MHz band to prevent high-frequency aliasing — which was the differential capacitor's job — so those capacitors are forced to be large.
- A differential capacitor is a single capacitor: however large it is, there is no second component for it to be mismatched against.
- A pair of large single-ended capacitors is different: real components have real tolerance, the two are never matched exactly, and that imbalance exacerbates the common-mode noise the filter was supposed to remove.
- Common-mode-only devices built this way, such as the OpenBCI Cyton, are working against their own input stage.

How Cerelog solved it on the V2 and 16-Channel boards:

- Montage selection was moved off the chip and onto physical hardware slider switches on the PCB.
- Users still swap freely between referential (SRB1) and differential (CH+/CH-) montage — the switches do it, not a register.
- Because the design no longer depends on the ADS1299 internal selector, Cerelog is free to build the filter arrangement TI actually recommends.
- The large capacitor was moved to the middle, differential position, where a tolerance mismatch has nothing to mismatch against and causes no harm.
- Smaller capacitors were placed inside the common-mode filters, where they belong.
- The result is dedicated common-mode filtering and dedicated differential filtering — both present, each doing only its own job.

Why it matters:

- This is the original optimized filtering arrangement that much of the BCI hardware industry was forced to design out in order to keep register-based montage switching.
- Cerelog restored it, allowing much stronger use of the ADS1299 IC's real potential: stronger common-mode rejection, proper anti-alias protection near 1 MHz, and no self-inflicted imbalance in the input stage.

## vs OpenBCI Cyton

| Feature | Cerelog ESP-EEG | OpenBCI Cyton |
|---|---|---|
| ADC | ADS1299 (24-bit) | ADS1299 (24-bit) |
| Wireless | Bluetooth Low Energy (BLE) and WiFi, both built-in | Requires WiFi Shield add-on |
| Noise reduction | True Closed-Loop Active Bias (DRL) | Passive bias |
| Battery charging | Onboard LiPo | Not included |
| USB | USB-C | Micro-USB |
| BrainFlow compatible | Yes | Yes |
| OpenBCI GUI compatible | Yes (forked) | Yes |
| Price | $389.99 USD (as of April 24, 2025) | Significantly higher |

## Services

Cerelog offers electronics engineering services:
- PCBA Design (mixed-signal, noise-sensitive boards)
- BCI Integration (TI ADS1299, AFE implementation)
- Embedded Firmware (C/C++, data acquisition, wireless communication)
- Product Customization (custom form factors, modified ESP-EEG designs)

## About

- Founded by an ex-SpaceX hardware design engineer
- Open source firmware and schematics on GitHub
- GitHub: https://github.com/Cerelog-ESP-EEG
- Twitter/X: https://twitter.com/CerelogOfficial
- LinkedIn: https://www.linkedin.com/company/cerelog
- YouTube: https://www.youtube.com/@Cerelog